wrap clkin init in r9 board check (#1307)
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@ -534,7 +534,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz)
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return bandwidth_hz_real != 0;
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}
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/*
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/*
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Configure PLL1 (Main MCU Clock) to max speed (204MHz).
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Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
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This function shall be called after cpu_clock_init().
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@ -811,10 +811,6 @@ void cpu_clock_init(void)
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// CCU2_CLK_APLL_CFG = 0;
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// CCU2_CLK_SDIO_CFG = 0;
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#endif
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkin_detect_init();
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}
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}
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clock_source_t activate_best_clock_source(void)
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@ -288,7 +288,11 @@ int main(void)
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}
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operacake_init(operacake_allow_gpio);
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clkin_detect_init();
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// FIXME: clock detection on r9 only works when calling init twice
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkin_detect_init();
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clkin_detect_init();
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}
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while (true) {
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transceiver_request_t request;
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