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wrap clkin init in r9 board check (#1307)

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This commit is contained in:
Jacob Graves
2023-04-19 11:32:32 -06:00
committed by GitHub
parent 464a6019b7
commit 189b5bf693
2 changed files with 6 additions and 6 deletions
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6
firmware/common/hackrf_core.c
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@ -534,7 +534,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz)
return bandwidth_hz_real != 0; return bandwidth_hz_real != 0;
} }
/* /*
Configure PLL1 (Main MCU Clock) to max speed (204MHz). Configure PLL1 (Main MCU Clock) to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init(). This function shall be called after cpu_clock_init().
@ -811,10 +811,6 @@ void cpu_clock_init(void)
// CCU2_CLK_APLL_CFG = 0; // CCU2_CLK_APLL_CFG = 0;
// CCU2_CLK_SDIO_CFG = 0; // CCU2_CLK_SDIO_CFG = 0;
#endif #endif
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
clkin_detect_init();
}
} }
clock_source_t activate_best_clock_source(void) clock_source_t activate_best_clock_source(void)

6
firmware/hackrf_usb/hackrf_usb.c
View File

@ -288,7 +288,11 @@ int main(void)
} }
operacake_init(operacake_allow_gpio); operacake_init(operacake_allow_gpio);
clkin_detect_init(); // FIXME: clock detection on r9 only works when calling init twice
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
clkin_detect_init();
clkin_detect_init();
}
while (true) { while (true) {
transceiver_request_t request; transceiver_request_t request;