diff --git a/firmware/sgpio/sgpio.c b/firmware/sgpio/sgpio.c
index 35e44e41..2b6b17d7 100644
--- a/firmware/sgpio/sgpio.c
+++ b/firmware/sgpio/sgpio.c
@@ -131,7 +131,7 @@ void test_sgpio_interface() {
 	}
 }
 
-void configure_sgpio() {
+void configure_sgpio_test_tx() {
 	// Disable all counters during configuration
 	SGPIO_CTRL_DISABLE = 0xFFFF;
 
@@ -144,9 +144,11 @@ void configure_sgpio() {
 
 	// Enable SGPIO pin outputs.
 	SGPIO_GPIO_OENREG =
-		(1L << 11) |    // direction
+		(1L << 11) |    // direction: TX: data to CPLD
 	    (1L << 10) |    // disable
-        0xFF;
+	    (0L <<  9) |    // capture
+	    (0L <<  8) |    // clock
+        0xFF;           // data: output
 
 	SGPIO_OUT_MUX_CFG( 8) = 0;   // SGPIO: Input: clock
 	SGPIO_OUT_MUX_CFG( 9) = 0;   // SGPIO: Input: qualifier
@@ -221,6 +223,71 @@ void configure_sgpio() {
     SGPIO_GPIO_OUTREG &= ~(1L << 10);
 }
 
+void configure_sgpio_test_rx() {
+	// Disable all counters during configuration
+	SGPIO_CTRL_DISABLE = 0xFFFF;
+
+    configure_sgpio_pin_functions();
+
+    // Set SGPIO output values.
+    SGPIO_GPIO_OUTREG =
+        (0L << 11) |    // direction
+        (1L << 10);     // disable
+
+	// Enable SGPIO pin outputs.
+	SGPIO_GPIO_OENREG =
+		(1L << 11) |    // direction: RX: data from CPLD
+	    (1L << 10) |    // disable
+	    (0L <<  9) |    // capture
+	    (0L <<  8) |    // clock
+        0x00;           // data: input
+
+	SGPIO_OUT_MUX_CFG( 8) = 0;   // SGPIO: Input: clock
+	SGPIO_OUT_MUX_CFG( 9) = 0;   // SGPIO: Input: qualifier
+    SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0);   // GPIO: Output: disable
+    SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0);   // GPIO: Output: direction
+
+	for(uint_fast8_t i=0; i<8; i++) {
+		SGPIO_OUT_MUX_CFG(i) =
+		    (0L <<  4) |    // P_OE_CFG = 0
+		    (9L <<  0);     // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
+	}
+
+	// Slice A
+	SGPIO_MUX_CFG(SGPIO_SLICE_A) =
+	    (0L << 12) |    // CONCAT_ORDER = 3 (8 slices)
+	    (0L << 11) |    // CONCAT_ENABLE = 0 (concatenate data)
+	    (0L <<  9) |    // QUALIFIER_SLICE_MODE = X
+	    (1L <<  7) |    // QUALIFIER_PIN_MODE = 1 (SGPIO9)
+	    (3L <<  5) |    // QUALIFIER_MODE = 3 (external SGPIO pin)
+	    (0L <<  3) |    // CLK_SOURCE_SLICE_MODE = X
+	    (0L <<  1) |    // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
+	    (1L <<  0);     // EXT_CLK_ENABLE = 1, external clock signal (slice)
+
+	SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
+	    (0L <<  8) |    // INV_QUALIFIER = 0 (use normal qualifier)
+	    (3L <<  6) |    // PARALLEL_MODE = 3 (shift 8 bits per clock)
+	    (0L <<  4) |    // DATA_CAPTURE_MODE = 0 (detect rising edge)
+	    (0L <<  3) |    // INV_OUT_CLK = 0 (normal clock)
+	    (1L <<  2) |    // CLKGEN_MODE = 1 (use external pin clock)
+	    (0L <<  1) |    // CLK_CAPTURE_MODE = 0 (use rising clock edge)
+	    (0L <<  0);     // MATCH_MODE = 0 (do not match data)
+
+	SGPIO_PRESET(SGPIO_SLICE_A) = 0;
+	SGPIO_COUNT(SGPIO_SLICE_A) = 0;
+	SGPIO_POS(SGPIO_SLICE_A) = (3 << 8) | (3 << 0);
+	SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE;     // Primary output data register
+	SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF;  // Shadow output data register
+    
+	// Start SGPIO operation by enabling slice clocks.
+    SGPIO_CTRL_ENABLE =
+        (1 << SGPIO_SLICE_A)
+    ;
+
+    // Enable codec data stream.
+    SGPIO_GPIO_OUTREG &= ~(1L << 10);
+}
+
 int main(void) {
 	pin_setup();
 	enable_1v8_power();
@@ -235,7 +302,7 @@ int main(void) {
 	gpio_set(PORT_LED1_3, (PIN_LED1 | PIN_LED2 | PIN_LED3)); /* LEDs on */
 
 	//test_sgpio_interface();
-	configure_sgpio();
+	configure_sgpio_test_rx();
 
 	while (1) {