From e12866f81ef482d05c2bf2526184cbc8e08d9020 Mon Sep 17 00:00:00 2001 From: Dominic Spill Date: Mon, 11 Feb 2019 16:38:07 -0700 Subject: [PATCH] Remove PLL1 low speed settings (it's out of spec) --- firmware/common/hackrf_core.c | 161 ++++++++++++------------------- firmware/common/hackrf_core.h | 2 - firmware/hackrf_usb/hackrf_usb.c | 2 - 3 files changed, 62 insertions(+), 103 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index 5ca74b7d..acda4280 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -146,9 +146,9 @@ i2c_bus_t i2c1 = { .transfer = i2c_lpc_transfer, }; -const i2c_lpc_config_t i2c_config_si5351c_slow_clock = { - .duty_cycle_count = 15, -}; +// const i2c_lpc_config_t i2c_config_si5351c_slow_clock = { +// .duty_cycle_count = 15, +// }; const i2c_lpc_config_t i2c_config_si5351c_fast_clock = { .duty_cycle_count = 255, @@ -463,6 +463,63 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) { return bandwidth_hz_real != 0; } +/* +Configure PLL1 (Main MCU Clock) to max speed (204MHz). +Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. +This function shall be called after cpu_clock_init(). +*/ +static void cpu_clock_pll1_max_speed(void) +{ + uint32_t pll_reg; + + /* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */ + /* Integer mode: + FCLKOUT = M*(FCLKIN/N) + FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N) + */ + pll_reg = CGU_PLL1_CTRL; + /* Clear PLL1 bits */ + pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */ + CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */ + CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */ + CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ + /* Set PLL1 up to 12MHz * 8 = 96MHz. */ + pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) + | CGU_PLL1_CTRL_PSEL(0) + | CGU_PLL1_CTRL_NSEL(0) + | CGU_PLL1_CTRL_MSEL(7) + | CGU_PLL1_CTRL_FBSEL(1); + CGU_PLL1_CTRL = pll_reg; + /* wait until stable */ + while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); + + /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ + CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1)); + + /* Wait before to switch to max speed */ + delay(WAIT_CPU_CLOCK_INIT_DELAY); + + /* Configure PLL1 Max Speed */ + /* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */ + pll_reg = CGU_PLL1_CTRL; + /* Clear PLL1 bits */ + pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */ + CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */ + CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */ + CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ + /* Set PLL1 up to 12MHz * 17 = 204MHz. */ + pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) + | CGU_PLL1_CTRL_PSEL(0) + | CGU_PLL1_CTRL_NSEL(0) + | CGU_PLL1_CTRL_MSEL(16) + | CGU_PLL1_CTRL_FBSEL(1) + | CGU_PLL1_CTRL_DIRECT(1); + CGU_PLL1_CTRL = pll_reg; + /* wait until stable */ + while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); + +} + /* clock startup for LPC4320 configure PLL1 to max speed (204MHz). Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ void cpu_clock_init(void) @@ -473,7 +530,7 @@ void cpu_clock_init(void) /* use IRC as clock source for APB3 */ CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC); - i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock); + i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock); si5351c_disable_all_outputs(&clock_gen); si5351c_disable_oeb_pin_control(&clock_gen); @@ -543,10 +600,7 @@ void cpu_clock_init(void) CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL); - cpu_clock_pll1_low_speed(); - - /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ - CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1)); + cpu_clock_pll1_max_speed(); /* use XTAL_OSC as clock source for PLL0USB */ CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) @@ -658,97 +712,6 @@ void cpu_clock_init(void) #endif } - -/* -Configure PLL1 to low speed (48MHz). -Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. -This function shall be called after cpu_clock_init(). -This function is mainly used to lower power consumption. -*/ -void cpu_clock_pll1_low_speed(void) -{ - uint32_t pll_reg; - - /* Configure PLL1 Clock (48MHz) */ - /* Integer mode: - FCLKOUT = M*(FCLKIN/N) - FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N) - */ - pll_reg = CGU_PLL1_CTRL; - /* Clear PLL1 bits */ - pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */ - CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */ - CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */ - CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ - /* Set PLL1 up to 12MHz * 4 = 48MHz. */ - pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) - | CGU_PLL1_CTRL_PSEL(0) - | CGU_PLL1_CTRL_NSEL(0) - | CGU_PLL1_CTRL_MSEL(3) - | CGU_PLL1_CTRL_FBSEL(1) - | CGU_PLL1_CTRL_DIRECT(1); - CGU_PLL1_CTRL = pll_reg; - /* wait until stable */ - while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); - - /* Wait a delay after switch to new frequency with Direct mode */ - delay(WAIT_CPU_CLOCK_INIT_DELAY); -} - -/* -Configure PLL1 (Main MCU Clock) to max speed (204MHz). -Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. -This function shall be called after cpu_clock_init(). -*/ -void cpu_clock_pll1_max_speed(void) -{ - uint32_t pll_reg; - - /* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */ - /* Integer mode: - FCLKOUT = M*(FCLKIN/N) - FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N) - */ - pll_reg = CGU_PLL1_CTRL; - /* Clear PLL1 bits */ - pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */ - CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */ - CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */ - CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ - /* Set PLL1 up to 12MHz * 8 = 96MHz. */ - pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) - | CGU_PLL1_CTRL_PSEL(0) - | CGU_PLL1_CTRL_NSEL(0) - | CGU_PLL1_CTRL_MSEL(7) - | CGU_PLL1_CTRL_FBSEL(1); - CGU_PLL1_CTRL = pll_reg; - /* wait until stable */ - while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); - - /* Wait before to switch to max speed */ - delay(WAIT_CPU_CLOCK_INIT_DELAY); - - /* Configure PLL1 Max Speed */ - /* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */ - pll_reg = CGU_PLL1_CTRL; - /* Clear PLL1 bits */ - pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */ - CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */ - CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */ - CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */ - /* Set PLL1 up to 12MHz * 17 = 204MHz. */ - pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) - | CGU_PLL1_CTRL_PSEL(0) - | CGU_PLL1_CTRL_NSEL(0) - | CGU_PLL1_CTRL_MSEL(16) - | CGU_PLL1_CTRL_FBSEL(1) - | CGU_PLL1_CTRL_DIRECT(1); - CGU_PLL1_CTRL = pll_reg; - /* wait until stable */ - while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)); - -} - void ssp1_set_mode_max2837(void) { spi_bus_start(max2837.bus, &ssp_config_max2837); diff --git a/firmware/common/hackrf_core.h b/firmware/common/hackrf_core.h index b30cfdff..3abded20 100644 --- a/firmware/common/hackrf_core.h +++ b/firmware/common/hackrf_core.h @@ -283,8 +283,6 @@ extern jtag_t jtag_cpld; extern i2c_bus_t i2c0; void cpu_clock_init(void); -void cpu_clock_pll1_low_speed(void); -void cpu_clock_pll1_max_speed(void); void ssp1_set_mode_max2837(void); void ssp1_set_mode_max5864(void); diff --git a/firmware/hackrf_usb/hackrf_usb.c b/firmware/hackrf_usb/hackrf_usb.c index 8bb8b417..cc102205 100644 --- a/firmware/hackrf_usb/hackrf_usb.c +++ b/firmware/hackrf_usb/hackrf_usb.c @@ -175,11 +175,9 @@ void usb_configuration_changed( set_transceiver_mode(TRANSCEIVER_MODE_OFF); if( device->configuration->number == 1 ) { // transceiver configuration - cpu_clock_pll1_max_speed(); led_on(LED1); } else { /* Configuration number equal 0 means usb bus reset. */ - cpu_clock_pll1_low_speed(); led_off(LED1); } }