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Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.

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Do conversion from unsigned to two's-compliment inside FPGA.
This commit is contained in:
Jared Boone
2013-11-16 13:29:00 -08:00
parent 9856ea3d14
commit 147f47a3f5
1 changed files with 10 additions and 4 deletions
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14
firmware/cpld/sgpio_if/top.vhd
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@ -93,7 +93,13 @@ begin
process(host_clk_i) process(host_clk_i)
begin begin
if rising_edge(host_clk_i) then if rising_edge(host_clk_i) then
data_to_host_o <= adc_data_i xor X"80"; if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"7f";
end if;
end if; end if;
end process; end process;
@ -101,14 +107,14 @@ begin
begin begin
if rising_edge(host_clk_i) then if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then if transfer_direction_i = to_dac then
dac_data_o <= (data_from_host_i xor X"80") & "00"; dac_data_o <= (data_from_host_i xor X"7f") & "11";
else else
dac_data_o <= (dac_data_o'high => '1', others => '0'); dac_data_o <= (dac_data_o'high => '0', others => '1');
end if; end if;
end if; end if;
end process; end process;
process(host_clk_i, codec_clk_i) process(host_clk_i)
begin begin
if rising_edge(host_clk_i) then if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then if transfer_direction_i = to_dac then