From 0efab1710a945500abbeedad9271f884854c15a8 Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Wed, 30 May 2012 07:33:23 +0200 Subject: [PATCH] Linker Script & New Startup to Load from SPIFI and Execute from RAM(SRAM). Start execution in SPIFI(ROM) and at startup, code from ROM is copied to RAM and shadow pointer is modified to RAM. So at end all the code and vector table is executed from RAM. --- firmware/blinky_SPIFI_SRAM/Makefile | 14 ++ firmware/blinky_SPIFI_SRAM/README | 3 + firmware/blinky_SPIFI_SRAM/blinky.c | 57 ++++++ firmware/common/LPC4330_M4_ROM_to_RAM.ld | 163 ++++++++++++++++++ .../common/LPC43xx_M4_Startup_ROM_to_RAM.c | 118 +++++++++++++ 5 files changed, 355 insertions(+) create mode 100644 firmware/blinky_SPIFI_SRAM/Makefile create mode 100644 firmware/blinky_SPIFI_SRAM/README create mode 100644 firmware/blinky_SPIFI_SRAM/blinky.c create mode 100644 firmware/common/LPC4330_M4_ROM_to_RAM.ld create mode 100644 firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c diff --git a/firmware/blinky_SPIFI_SRAM/Makefile b/firmware/blinky_SPIFI_SRAM/Makefile new file mode 100644 index 00000000..cb4e8725 --- /dev/null +++ b/firmware/blinky_SPIFI_SRAM/Makefile @@ -0,0 +1,14 @@ +# Hey Emacs, this is a -*- makefile -*- + +# Target file name (without extension). +TARGET = blinky + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c \ + $(LIBS_PATH)/LPC43xx_M4_Startup_ROM_to_RAM.c \ + $(LIBS_PATH)/LPC43xx_M4_Interrupts.c \ + $(LIBS_PATH)/hackrf_core.c + +# Override Linker Script +LINKER_SCRIPT = LPC4330_M4_ROM_to_RAM.ld +include ../common/Makefile_inc.mk diff --git a/firmware/blinky_SPIFI_SRAM/README b/firmware/blinky_SPIFI_SRAM/README new file mode 100644 index 00000000..79251aaf --- /dev/null +++ b/firmware/blinky_SPIFI_SRAM/README @@ -0,0 +1,3 @@ +This is the simplest example firmware for HackRF. It flashes three LEDs. +This Example Start execution in SPIFI(ROM) and at startup, code from ROM is copied to RAM and shadow pointer is modified to RAM. +So at end all the code and vector table is executed from RAM. diff --git a/firmware/blinky_SPIFI_SRAM/blinky.c b/firmware/blinky_SPIFI_SRAM/blinky.c new file mode 100644 index 00000000..7fa09249 --- /dev/null +++ b/firmware/blinky_SPIFI_SRAM/blinky.c @@ -0,0 +1,57 @@ +/* + * Copyright 2010 - 2012 Michael Ossmann + * + * This file is part of HackRF. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include "hackrf_core.h" + +void wait(uint8_t duration) +{ + volatile uint32_t i; + for (i = 0; i < duration * 1000000; i++); +} + +uint32_t boot0, boot1, boot2, boot3; + +int main() +{ + + gpio_init(); + + EN1V8_SET; + EN1V8_CLR; + + while (1) { + boot0 = BOOT0; + boot1 = BOOT1; + boot2 = BOOT2; + boot3 = BOOT3; + + LED1_SET; + LED2_SET; + LED3_SET; + wait(1); + LED1_CLR; + LED2_CLR; + LED3_CLR; + wait(1); + } + + return 0 ; +} diff --git a/firmware/common/LPC4330_M4_ROM_to_RAM.ld b/firmware/common/LPC4330_M4_ROM_to_RAM.ld new file mode 100644 index 00000000..6d9d92e7 --- /dev/null +++ b/firmware/common/LPC4330_M4_ROM_to_RAM.ld @@ -0,0 +1,163 @@ +/* + * Copyright 2010 - 2012 Michael Ossmann + * Copyright 2012 Benjamin Vernoux + * + * This file is part of HackRF + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) +GROUP(libgcc.a libc.a libm.a libnosys.a) + +MEMORY +{ + /* + * Our code is installed in SPIFI(ROM) at 0x80000000 it is addressed through the 256M shadow area at 0x00000000 at Boot. + * Reset_Handler call Reset_Handler_ROM_to_RAM(executed in SPIFI) and Copy the code from ROM to RAM, + * and set shadow pointer to RAM, then the code execution continue in RAM. + */ + rom (rx) : ORIGIN = 0x80000000, LENGTH = 128K /* Real ROM Address It cannot exceed RAM size (Real Size is 1MB) */ + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K /* Real RAM Address */ + shadow_ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128K /* 128 Kb Real Address is 0x10000000 but remapped to Shadow 0x00000000 */ + + /* there are some additional RAM regions */ +} + +/* + * much copied from: Linker script for Cortex-M3 + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +EXTERN(Reset_Handler) +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _text_ram = . + ORIGIN(ram); /* Start of Code in RAM */ + + . = ALIGN(0x400); /* Ensure that vector table is aligned as hardware requires. */ + _interrupt_vector_table = .; + KEEP(*(.irq_handler_table)) + + *(.text .text.* .gnu.linkonce.t.*) + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(8); + _etext = .; + } > shadow_ram + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > shadow_ram + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > shadow_ram + __exidx_end = .; + + _etext = .; + _etext_ram = . + ORIGIN(ram); + _etext_rom = . + ORIGIN(rom); + + .data : + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > shadow_ram + + /* zero initialized data */ + .bss : + { + _bss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + _ebss = .; + __bss_end__ = .; + } > shadow_ram + + /* Where we put the heap with cr_clib */ + .cr_heap : + { + end = .; + __end__ = .; + _pvHeapStart = .; + } > shadow_ram + + /* Leave room above stack for IAP to run */ + _StackTop = ORIGIN(ram) + (ORIGIN(shadow_ram) + LENGTH(shadow_ram) - 32); + +} diff --git a/firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c b/firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c new file mode 100644 index 00000000..50d9e234 --- /dev/null +++ b/firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c @@ -0,0 +1,118 @@ +/* + * Copyright 2012 Benjamin Vernoux + * + * This file is part of HackRF. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ +/* + Copyright 2010-07 By Opendous Inc. (www.MicropendousX.org) + NVIC handler info copied from NXP User Manual UM10360 + + Start-up code for LPC17xx. See TODOs for + modification instructions. + + Permission to use, copy, modify, and distribute this software + and its documentation for any purpose and without fee is hereby + granted, provided that the above copyright notice appear in all + copies and that both that the copyright notice and this + permission notice and warranty disclaimer appear in supporting + documentation, and that the name of the author not be used in + advertising or publicity pertaining to distribution of the + software without specific, written prior permission. + + The author disclaim all warranties with regard to this + software, including all implied warranties of merchantability + and fitness. In no event shall the author be liable for any + special, indirect or consequential damages or any damages + whatsoever resulting from loss of use, data or profits, whether + in an action of contract, negligence or other tortious action, + arising out of or in connection with the use or performance of + this software. +*/ + +#include + +#define CREG_BASE 0x40043000 +#define MMIO32(addr) (*(volatile unsigned long *)(addr)) +#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100) + +/* Reset_Handler_ROM_to_RAM variables defined in linker script */ +extern unsigned long _text_ram; /* Correspond to start of Code in RAM */ +extern unsigned long _etext_ram; /* Correspond to end of Code in RAM */ +extern unsigned long _etext_rom; /* Correspond to end of Code in ROM */ + + +/* Reset_Handler variables defined in linker script */ +extern unsigned long _interrupt_vector_table; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _etext; +extern unsigned long _bss; +extern unsigned long _ebss; + +extern void __libc_init_array(void); +extern int main(void); + +/* Code to be Copied from ROM to RAM */ +void Reset_Handler_ROM_to_RAM(void) +{ + unsigned long *src, *dest; + + // Copy the code from ROM to Real RAM + src = &_etext_rom-(&_etext_ram-&_text_ram); + for(dest = &_text_ram; dest < &_etext_ram; ) + { + *dest++ = *src++; + } + + /* Change Shadow memory to Real RAM */ + CREG_M4MEMMAP = &_text_ram; + + /* Continue Execution in RAM */ +} + +/* Reset Handler */ +void Reset_Handler(void) +{ + unsigned long *src, *dest; + + Reset_Handler_ROM_to_RAM(); + + // Copy the data segment initializers from flash to SRAM + src = &_etext; + for(dest = &_data; dest < &_edata; ) + { + *dest++ = *src++; + } + + // Initialize the .bss segment of memory to zeros + src = &_bss; + while (src < &_ebss) + { + *src++ = 0; + } + + __libc_init_array(); + + // Set the vector table location. + SCB_VTOR = &_interrupt_vector_table; + + main(); + + // In case main() fails, have something to breakpoint + while (1) {;} +}