Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD.
This commit is contained in:
Jared Boone
2006
hardware/jellybean/sgpio_if/sgpio_if.svf
Executable file
2006
hardware/jellybean/sgpio_if/sgpio_if.svf
Executable file
File diff suppressed because it is too large
Load Diff
242
hardware/jellybean/sgpio_if/sgpio_if.xise
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242
hardware/jellybean/sgpio_if/sgpio_if.xise
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||||||
|
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
<!-- -->
|
||||||
|
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||||
|
<!-- -->
|
||||||
|
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|top_tb|behavior" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_DesignName" xil_pn:value="sgpio_test" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||||
|
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-29T12:49:49" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8998E598855F452AB5BAE34A005D4FD5" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||||
|
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||||
|
</properties>
|
||||||
|
|
||||||
|
<bindings/>
|
||||||
|
|
||||||
|
<libraries/>
|
||||||
|
|
||||||
|
<autoManagedFiles>
|
||||||
|
<!-- The following files are identified by `include statements in verilog -->
|
||||||
|
<!-- source files and are automatically managed by Project Navigator. -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||||
|
<!-- project is analyzed based on files automatically identified as -->
|
||||||
|
<!-- include files. -->
|
||||||
|
</autoManagedFiles>
|
||||||
|
|
||||||
|
</project>
|
||||||
126
hardware/jellybean/sgpio_if/top.ucf
Executable file
126
hardware/jellybean/sgpio_if/top.ucf
Executable file
@ -0,0 +1,126 @@
|
|||||||
|
#
|
||||||
|
# Copyright 2012 Jared Boone
|
||||||
|
#
|
||||||
|
# This file is part of HackRF.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
# any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; see the file COPYING. If not, write to
|
||||||
|
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||||
|
# Boston, MA 02110-1301, USA.
|
||||||
|
|
||||||
|
NET "CODEC_CLK" LOC="22" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "CODEC_X2_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
#NET "GCLK2" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
|
||||||
|
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
|
||||||
|
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
|
||||||
|
|
||||||
|
NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
|
||||||
|
NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
|
||||||
|
NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18;
|
||||||
|
|
||||||
|
#NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
#NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
#NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
#NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DIRECTION" LOC="71" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DISABLE" LOC="76" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_CAPTURE" LOC="91" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_CLK" LOC="68" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "HOST_DATA<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
|
||||||
|
NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33;
|
||||||
|
|
||||||
|
INST "DA<0>" TNM=adc_data;
|
||||||
|
INST "DA<1>" TNM=adc_data;
|
||||||
|
INST "DA<2>" TNM=adc_data;
|
||||||
|
INST "DA<3>" TNM=adc_data;
|
||||||
|
INST "DA<4>" TNM=adc_data;
|
||||||
|
INST "DA<5>" TNM=adc_data;
|
||||||
|
INST "DA<6>" TNM=adc_data;
|
||||||
|
INST "DA<7>" TNM=adc_data;
|
||||||
|
|
||||||
|
TIMESPEC "TS_adc_data" = FROM "adc_data" TO "CODEC_X2_CLK" 16 ns;
|
||||||
|
|
||||||
|
INST "DD<0>" TNM=dac_data;
|
||||||
|
INST "DD<1>" TNM=dac_data;
|
||||||
|
INST "DD<2>" TNM=dac_data;
|
||||||
|
INST "DD<3>" TNM=dac_data;
|
||||||
|
INST "DD<4>" TNM=dac_data;
|
||||||
|
INST "DD<5>" TNM=dac_data;
|
||||||
|
INST "DD<6>" TNM=dac_data;
|
||||||
|
INST "DD<7>" TNM=dac_data;
|
||||||
|
INST "DD<8>" TNM=dac_data;
|
||||||
|
INST "DD<9>" TNM=dac_data;
|
||||||
|
|
||||||
|
TIMESPEC "TS_dac_data" = FROM "CODEC_X2_CLK" TO "dac_data" 15 ns;
|
||||||
|
|
||||||
|
INST "HOST_DATA<7>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<6>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<5>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<4>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<3>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<2>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<1>" TNM=to_host;
|
||||||
|
INST "HOST_DATA<0>" TNM=to_host;
|
||||||
|
INST "HOST_CAPTURE" TNM=to_host;
|
||||||
|
|
||||||
|
#TIMESPEC "TS_to_host" = FROM "to_host" TO "HOST_CLK" 6 ns;
|
||||||
|
#TIMEGRP "to_host" OFFSET=OUT 6 ns AFTER "HOST_CLK";
|
||||||
132
hardware/jellybean/sgpio_if/top.vhd
Executable file
132
hardware/jellybean/sgpio_if/top.vhd
Executable file
@ -0,0 +1,132 @@
|
|||||||
|
--
|
||||||
|
-- Copyright 2012 Jared Boone
|
||||||
|
--
|
||||||
|
-- This file is part of HackRF.
|
||||||
|
--
|
||||||
|
-- This program is free software; you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
-- any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program; see the file COPYING. If not, write to
|
||||||
|
-- the Free Software Foundation, Inc., 51 Franklin Street,
|
||||||
|
-- Boston, MA 02110-1301, USA.
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.vcomponents.all;
|
||||||
|
|
||||||
|
entity top is
|
||||||
|
Port(
|
||||||
|
HOST_DATA : inout std_logic_vector(7 downto 0);
|
||||||
|
HOST_CLK : out std_logic;
|
||||||
|
HOST_CAPTURE : out std_logic;
|
||||||
|
HOST_DISABLE : in std_logic;
|
||||||
|
HOST_DIRECTION : in std_logic;
|
||||||
|
|
||||||
|
DA : in std_logic_vector(7 downto 0);
|
||||||
|
DD : out std_logic_vector(9 downto 0);
|
||||||
|
|
||||||
|
CODEC_CLK : in std_logic;
|
||||||
|
CODEC_X2_CLK : in std_logic;
|
||||||
|
|
||||||
|
B1AUX : inout std_logic_vector(16 downto 9);
|
||||||
|
B2AUX : inout std_logic_vector(16 downto 1)
|
||||||
|
);
|
||||||
|
|
||||||
|
end top;
|
||||||
|
|
||||||
|
architecture Behavioral of top is
|
||||||
|
signal codec_clk_i : std_logic;
|
||||||
|
signal adc_data_i : std_logic_vector(7 downto 0);
|
||||||
|
signal dac_data_o : std_logic_vector(9 downto 0);
|
||||||
|
|
||||||
|
signal host_clk_i : std_logic;
|
||||||
|
signal host_clk_o : std_logic;
|
||||||
|
|
||||||
|
type transfer_direction is (from_adc, to_dac);
|
||||||
|
signal transfer_direction_i : transfer_direction;
|
||||||
|
|
||||||
|
signal host_data_enable_i : std_logic;
|
||||||
|
signal host_data_capture_o : std_logic;
|
||||||
|
|
||||||
|
signal data_from_host_i : std_logic_vector(7 downto 0);
|
||||||
|
signal data_to_host_o : std_logic_vector(7 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
B1AUX <= (others => '0');
|
||||||
|
B2AUX <= (others => '0');
|
||||||
|
|
||||||
|
------------------------------------------------
|
||||||
|
-- Codec interface
|
||||||
|
|
||||||
|
adc_data_i <= DA(7 downto 0);
|
||||||
|
DD(9 downto 0) <= dac_data_o;
|
||||||
|
|
||||||
|
------------------------------------------------
|
||||||
|
-- Clocks
|
||||||
|
|
||||||
|
codec_clk_i <= CODEC_CLK;
|
||||||
|
|
||||||
|
BUFG_host : BUFG
|
||||||
|
port map (
|
||||||
|
O => host_clk_i,
|
||||||
|
I => CODEC_X2_CLK
|
||||||
|
);
|
||||||
|
|
||||||
|
------------------------------------------------
|
||||||
|
-- SGPIO interface
|
||||||
|
|
||||||
|
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
|
||||||
|
else (others => 'Z');
|
||||||
|
data_from_host_i <= HOST_DATA;
|
||||||
|
|
||||||
|
HOST_CLK <= host_clk_o;
|
||||||
|
HOST_CAPTURE <= host_data_capture_o;
|
||||||
|
host_data_enable_i <= not HOST_DISABLE;
|
||||||
|
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
|
||||||
|
else from_adc;
|
||||||
|
|
||||||
|
------------------------------------------------
|
||||||
|
|
||||||
|
host_clk_o <= host_clk_i;
|
||||||
|
|
||||||
|
------------------------------------------------
|
||||||
|
|
||||||
|
process(host_clk_i)
|
||||||
|
begin
|
||||||
|
if rising_edge(host_clk_i) then
|
||||||
|
data_to_host_o <= adc_data_i;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(host_clk_i)
|
||||||
|
begin
|
||||||
|
if rising_edge(host_clk_i) then
|
||||||
|
if transfer_direction_i = to_dac then
|
||||||
|
dac_data_o <= data_from_host_i & "00";
|
||||||
|
else
|
||||||
|
dac_data_o <= (dac_data_o'high => '1', others => '0');
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(host_clk_i, codec_clk_i)
|
||||||
|
begin
|
||||||
|
if rising_edge(host_clk_i) then
|
||||||
|
if codec_clk_i = '1' then
|
||||||
|
host_data_capture_o <= host_data_enable_i;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end Behavioral;
|
||||||
138
hardware/jellybean/sgpio_if/top_tb.vhd
Executable file
138
hardware/jellybean/sgpio_if/top_tb.vhd
Executable file
@ -0,0 +1,138 @@
|
|||||||
|
--
|
||||||
|
-- Copyright 2012 Jared Boone
|
||||||
|
--
|
||||||
|
-- This file is part of HackRF.
|
||||||
|
--
|
||||||
|
-- This program is free software; you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
-- any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program; see the file COPYING. If not, write to
|
||||||
|
-- the Free Software Foundation, Inc., 51 Franklin Street,
|
||||||
|
-- Boston, MA 02110-1301, USA.
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
|
||||||
|
ENTITY top_tb IS
|
||||||
|
END top_tb;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF top_tb IS
|
||||||
|
|
||||||
|
COMPONENT top
|
||||||
|
PORT(
|
||||||
|
HOST_DATA : INOUT std_logic_vector(7 downto 0);
|
||||||
|
HOST_CLK : OUT std_logic;
|
||||||
|
HOST_CAPTURE : OUT std_logic;
|
||||||
|
HOST_DISABLE : IN std_logic;
|
||||||
|
HOST_DIRECTION : IN std_logic;
|
||||||
|
DA : IN std_logic_vector(7 downto 0);
|
||||||
|
DD : OUT std_logic_vector(9 downto 0);
|
||||||
|
CODEC_CLK : IN std_logic;
|
||||||
|
CODEC_X2_CLK : IN std_logic;
|
||||||
|
B1AUX : INOUT std_logic_vector(16 downto 9);
|
||||||
|
B2AUX : INOUT std_logic_vector(16 downto 1)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
--Inputs
|
||||||
|
signal DA : std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
signal CODEC_CLK : std_logic := '0';
|
||||||
|
signal CODEC_X2_CLK : std_logic := '0';
|
||||||
|
signal HOST_DISABLE : std_logic := '1';
|
||||||
|
signal HOST_DIRECTION : std_logic := '0';
|
||||||
|
|
||||||
|
--BiDirs
|
||||||
|
signal HOST_DATA : std_logic_vector(7 downto 0);
|
||||||
|
signal B1AUX : std_logic_vector(16 downto 9);
|
||||||
|
signal B2AUX : std_logic_vector(16 downto 1);
|
||||||
|
|
||||||
|
--Outputs
|
||||||
|
signal DD : std_logic_vector(9 downto 0);
|
||||||
|
signal HOST_CLK : std_logic;
|
||||||
|
signal HOST_CAPTURE : std_logic;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
uut: top PORT MAP (
|
||||||
|
HOST_DATA => HOST_DATA,
|
||||||
|
HOST_CLK => HOST_CLK,
|
||||||
|
HOST_CAPTURE => HOST_CAPTURE,
|
||||||
|
HOST_DISABLE => HOST_DISABLE,
|
||||||
|
HOST_DIRECTION => HOST_DIRECTION,
|
||||||
|
DA => DA,
|
||||||
|
DD => DD,
|
||||||
|
CODEC_CLK => CODEC_CLK,
|
||||||
|
CODEC_X2_CLK => CODEC_X2_CLK,
|
||||||
|
B1AUX => B1AUX,
|
||||||
|
B2AUX => B2AUX
|
||||||
|
);
|
||||||
|
|
||||||
|
clk_process :process
|
||||||
|
begin
|
||||||
|
CODEC_CLK <= '1';
|
||||||
|
CODEC_X2_CLK <= '1';
|
||||||
|
wait for 12.5 ns;
|
||||||
|
CODEC_X2_CLK <= '0';
|
||||||
|
wait for 12.5 ns;
|
||||||
|
CODEC_CLK <= '0';
|
||||||
|
CODEC_X2_CLK <= '1';
|
||||||
|
wait for 12.5 ns;
|
||||||
|
CODEC_X2_CLK <= '0';
|
||||||
|
wait for 12.5 ns;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
adc_proc: process
|
||||||
|
begin
|
||||||
|
wait until rising_edge(CODEC_CLK);
|
||||||
|
wait for 9 ns;
|
||||||
|
DA <= (others => '0');
|
||||||
|
|
||||||
|
wait until falling_edge(CODEC_CLK);
|
||||||
|
wait for 9 ns;
|
||||||
|
DA <= (others => '1');
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
sgpio_proc: process
|
||||||
|
begin
|
||||||
|
HOST_DATA <= (others => 'Z');
|
||||||
|
|
||||||
|
HOST_DIRECTION <= '0';
|
||||||
|
HOST_DISABLE <= '1';
|
||||||
|
|
||||||
|
wait for 135 ns;
|
||||||
|
|
||||||
|
HOST_DISABLE <= '0';
|
||||||
|
|
||||||
|
wait for 1000 ns;
|
||||||
|
|
||||||
|
HOST_DISABLE <= '1';
|
||||||
|
|
||||||
|
wait for 100 ns;
|
||||||
|
|
||||||
|
HOST_DIRECTION <= '1';
|
||||||
|
|
||||||
|
wait for 100 ns;
|
||||||
|
|
||||||
|
HOST_DISABLE <= '0';
|
||||||
|
|
||||||
|
for i in 0 to 10 loop
|
||||||
|
HOST_DATA <= (others => '0');
|
||||||
|
wait until rising_edge(host_clk) and HOST_CAPTURE = '1';
|
||||||
|
|
||||||
|
HOST_DATA <= (others => '1');
|
||||||
|
wait until rising_edge(host_clk) and HOST_CAPTURE = '1';
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
||||||
Reference in New Issue
Block a user