From 02f61f4d64c9f0be0f945bc0287f22f0fd236a77 Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Wed, 13 Jun 2012 17:53:10 -0700
Subject: [PATCH] Added r_div argument to si5351c_configure_multisynth().
 Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to
 CPLD (both inverted and non-inverted).

---
 firmware/common/si5351c.c | 27 +++++++++++++++++++++------
 firmware/common/si5351c.h |  3 ++-
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c
index 0c3fa1fc..d6538218 100644
--- a/firmware/common/si5351c.c
+++ b/firmware/common/si5351c.c
@@ -132,7 +132,8 @@ void si5351c_configure_pll1_multisynth()
 }
 
 void si5351c_configure_multisynth( const uint_fast8_t ms_number,
-    	const uint32_t p1, const uint32_t p2, const uint32_t p3)
+    	const uint32_t p1, const uint32_t p2, const uint32_t p3,
+    	const uint_fast8_t r_div)
 {
 	/*
 	 * TODO: Check for p3 > 0? 0 has no meaning in fractional mode?
@@ -143,7 +144,7 @@ void si5351c_configure_multisynth( const uint_fast8_t ms_number,
 			register_number,
 			(p3 >> 8) & 0xFF,
 			(p3 >> 0) & 0xFF,
-			(0 << 4) | (0 << 2) | ((p1 >> 16) & 0x3),
+			(r_div << 4) | (0 << 2) | ((p1 >> 16) & 0x3),
 			(p1 >> 8) & 0xFF,
 			(p1 >> 0) & 0xFF,
 			(((p3 >> 16) & 0xF) << 4) | (((p2 >> 16) & 0xF) << 0),
@@ -166,8 +167,22 @@ void si5351c_configure_multisynth( const uint_fast8_t ms_number,
  *   MS1_INT=1 (integer mode)
  *   MS1_SRC=0 (PLLA as source for MultiSynth 1)
  *   CLK1_INV=0 (not inverted)
- *   CLK1_SRC=3 (MS1 as input source)
+ *   CLK1_SRC=2 (MS1 as input source)
  *   CLK1_IDRV=3 (8mA)
+ * CLK2:
+ *   CLK2_PDN=0 (powered up)
+ *   MS2_INT=1 (integer mode)
+ *   MS2_SRC=0 (PLLA as source for MultiSynth 2)
+ *   CLK2_INV=0 (not inverted)
+ *   CLK2_SRC=2 (MS0 as input source)
+ *   CLK2_IDRV=3 (8mA)
+ * CLK3:
+ *   CLK3_PDN=0 (powered up)
+ *   MS3_INT=1 (integer mode)
+ *   MS3_SRC=0 (PLLA as source for MultiSynth 3)
+ *   CLK3_INV=1 (inverted)
+ *   CLK3_SRC=2 (MS0 as input source)
+ *   CLK3_IDRV=3 (8mA)
  * CLK4:
  *   CLK4_PDN=0 (powered up)
  *   MS4_INT=0 (fractional mode -- to support 12MHz to LPC for USB DFU)
@@ -178,13 +193,13 @@ void si5351c_configure_multisynth( const uint_fast8_t ms_number,
  */
 void si5351c_configure_clock_control()
 {
-	uint8_t data[] = { 16, 0x4F, 0x4F, 0x80, 0x80, 0x0F, 0x80, 0x80, 0x80 };
+	uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x5B, 0x0F, 0x80, 0x80, 0x80 };
 	si5351c_write(data, sizeof(data));
 }
 
-/* Enable CLK outputs 0, 1, 4 only. */
+/* Enable CLK outputs 0, 1, 2, 3, 4 only. */
 void si5351c_enable_clock_outputs()
 {
-	uint8_t data[] = { 3, 0xEC };
+	uint8_t data[] = { 3, 0xE0 };
 	si5351c_write(data, sizeof(data));
 }
diff --git a/firmware/common/si5351c.h b/firmware/common/si5351c.h
index e847852c..c887309d 100644
--- a/firmware/common/si5351c.h
+++ b/firmware/common/si5351c.h
@@ -40,7 +40,8 @@ void si5351c_enable_xo_and_ms_fanout();
 void si5351c_configure_pll_sources_for_xtal();
 void si5351c_configure_pll1_multisynth();
 void si5351c_configure_multisynth( const uint_fast8_t ms_number,
-    	const uint32_t p1, const uint32_t p2, const uint32_t p3);
+    	const uint32_t p1, const uint32_t p2, const uint32_t p3,
+    	const uint_fast8_t r_div);
 void si5351c_configure_clock_control();
 void si5351c_enable_clock_outputs();